Critical Chip-Level Examination on GAA Technology with Dual-sided Interconnects from BSPDN to Backside Clock: Architecture Innovations, PPA and First Signal/Power Integrity Analysis

Published in 2026 IEEE Silicon Nanoelectronics Workshop (SNW), Hilton Hawaiian Village, Honolulu, HI, USA, 2026

Feiyu Teng, Xiangyu Yan, Wanyue Peng, Jiacheng Sun, Haoran Lu, Yanbang Chu, Mingmin Lin, Chuangxin Zhou, Xun Jiang, Xiang Li, Jianxiang Jin, Kairong Guo, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ming Li, and Heng Wu