About Me
EDA for next-generation integrated-circuit design
I am currently a Ph.D. student at the School of Integrated Circuits, Peking University, advised by Prof. Yibo Lin. My research interests focus on Electronic Design Automation, specifically in Physical Design and Custom Design.
Standard-cell layout synthesis DTCO for emerging devices
My Chinese name is Guo Kairong 郭铠荣
Publications
Conference Papers
- C7EPiCell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction † Equal contribution. 63rd Design Automation Conference (DAC), Long Beach, CA, USA, 2026 PDF
- C6FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction 43rd International Conference on Machine Learning (ICML), Seoul, South Korea, 2026 PDF
- C5Critical Chip-Level Examination on GAA Technology with Dual-sided Interconnects from BSPDN to Backside Clock: Architecture Innovations, PPA and First Signal/Power Integrity Analysis 2026 IEEE Silicon Nanoelectronics Workshop (SNW), Hilton Hawaiian Village, Honolulu, HI, USA, 2026
- C4CAPCell: Standard Cell Layout Synthesis with Parasitic Capacitance Aware Parallel Sampling International Symposium of Electronics Design Automation (ISEDA), Singapore, 2026 PDF
- C3Standard Cell Layout Synthesis for Dual-Sided 3D-Stacked Transistors 31st Asia and South Pacific Design Automation Conference (ASP-DAC), Lantau, Hong Kong, 2026 PDF
- C2Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, 2025 PDF
- C1Multi-Row Standard Cell Layout Synthesis with Enhanced Scalability International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025 PDF
Experience
Education
- 2025 - PresentPh.D. in Integrated Circuits Peking University (PKU) Beijing, China
- 2021 - 2025B.S. in Microelectronics Beihang University (BUAA) Beijing, China
