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Multi-Row Standard Cell Layout Synthesis with Enhanced Scalability
Published in International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025
Kairong Guo, Yibo Lin
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization
Published in 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, 2025
Yi Ren, Baokang Peng, Chenhao Xue, Kairong Guo, Yukun Wang, Guoyao Cheng, Yibo Lin, Lining Zhang, Guangyu Sun
Standard Cell Layout Synthesis for Dual-Sided 3D-Stacked Transistors
Published in 31st Asia and South Pacific Design Automation Conference (ASP-DAC), Lantau, Hong Kong, 2026
Kairong Guo, Haoran Lu, Rui Guo, Jiarui Wang, Chunyuan Zhao, Heng Wu, Runsheng Wang, Yibo Lin
CAPCell: Standard Cell Layout Synthesis with Parasitic Capacitance Aware Parallel Sampling
Published in International Symposium of Electronics Design Automation (ISEDA), Singapore, 2026
Kairong Guo, Jiechen Huang, Wenjian Yu, Yibo Lin
Critical Chip-Level Examination on GAA Technology with Dual-sided Interconnects from BSPDN to Backside Clock: Architecture Innovations, PPA and First Signal/Power Integrity Analysis
Published in 2026 IEEE Silicon Nanoelectronics Workshop (SNW), Hilton Hawaiian Village, Honolulu, HI, USA, 2026
Feiyu Teng, Xiangyu Yan, Wanyue Peng, Jiacheng Sun, Haoran Lu, Yanbang Chu, Mingmin Lin, Chuangxin Zhou, Xun Jiang, Xiang Li, Jianxiang Jin, Kairong Guo, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ming Li, and Heng Wu
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
Published in 43rd International Conference on Machine Learning (ICML), Seoul, South Korea, 2026
Haoyi Zhang, Kairong Guo, Bojie Zhang, Yibo Lin, Runsheng Wang
EPiCell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction
Published in 63rd Design Automation Conference (DAC), Long Beach, CA, USA, 2026
Wenbo An†, Kairong Guo†, Haoyi Zhang, Yibo Lin
† Equal contribution.